namespace UnityPeripherals.Lowlevel

type 't expr = 't Stdlib.Asyncseq.expr

open Stdlib.Asyncseq

module Varargs =
  val make2 : _ expr -> _ expr -> string
  val double_to_int : precision:int -> System.Double expr -> int expr

/// <summary>
/// <c>Stdenv</c> is the standard environment of an embedded program.
/// </summary>
module Stdenv =
  open Frduino.Lib.Async

  /// <summary>
  /// <c>Stdenv.clock t</c> is the system clock (used to access concepts of time and intervals).
  /// </summary>
  val clock : env -> clock

/// <summary>
/// <c>Async</c> is for composing non-linear computation sequences.
/// </summary>
module Async =
  open Frduino.Lib.Async

  /// <summary>
  /// <c>Async.sleep for_clock millis</c> requests a delay in the asynchronous workflow for a duration of <c>milis</c> milliseconds.
  /// </summary>
  /// <param name="for_clock">A capacity for the system's clock.</param>
  /// <param name="millis">The duration of delay, in millisecond integer.</param>
  /// <returns>There is no logical value to return, but this function still returns a wait handler to await for the completion of this asynchronous computation.</returns>
  val sleep : clock -> (int expr -> Asyn<unit>)

module Math =
  module Double =
    type double = System.Double
    val atan: double expr -> double expr
    val sqrt: double expr -> double expr
    val add : double expr -> double expr -> double expr
    val mul : double expr -> double expr -> double expr
    val div : double expr -> double expr -> double expr
    module Syntax =
      val ( +. ) : double expr -> double expr -> double expr
      val ( *. ) : double expr -> double expr -> double expr
      val ( /. ) : double expr -> double expr -> double expr

  module Int =
    val add : int expr -> int expr -> int expr

namespace UnityPeripherals.Lowlevel

open Stdlib.Asyncseq
open Frduino

type wireable' = Lib.Wire.wireable'

type wireable<'t when 't :> wireable' and 't : (new : unit -> 't)> = Lib.Wire.wireable<'t>

/// <summary>
/// <c>Wire</c> is a library for communicating between a network of multi-master, multi-slave devices.
/// </summary>
/// <remark>
/// This is abstraction over protocols such as I2C, etc.
/// </remark>
module Wire =
  open Frduino.Lib.Wire

  val with_open_1<'W, 'T, 'K when wireable<'W>> : (t<'W> -> M<'T, 'K>) -> M<'T, 'K>

  /// <summary>
  /// Serialize by <c>Wire.Buf_write</c>'ing to ensure speed and memory efficiency.
  /// </summary>
  module Buf_write =

    /// <summary>
    /// <c>Buf_write.with_trnsms flow_of_dev</c> is a buffered writer backed by <c>flow_of_dev</c>.
    /// </summary>
    /// <returns>
    /// </returns>
    val with_trnms<'W when wireable<'W>> : t<'W> -> (writer<'W> -> Asyn<unit>) -> Asyn<unit>

    /// <summary>
    /// <c>Buf_write.byte to_ b</c> copies <c>b</c> into the serializer's internal buffer.
    /// </summary>
    val byte<'W when wireable<'W>> : writer<'W> -> int expr -> Asyn<unit>

  /// <summary>
  /// A <c>Wire.Flow</c> can be used to read or write bytes.
  /// </summary>
  // module Flow =
  //   val copy_string

  /// <summary>
  /// <c>Wire.Request_for</c> pokes a target device then parses an incoming packet of consecutive bytes.
  /// </summary>
  module Request_for =
    val n_from<'W when wireable<'W>> : int -> t<'W> -> asyn_n<int>

namespace UnityPeripherals.Lowlevel

module Bitvec =
  open Stdlib.Asyncseq
  open Frduino.Lib.Bitvec

  val sll : shamount:int expr -> x:t expr -> t expr
  val or' : x:t expr -> y:t expr -> t expr

module Io =
  open Stdlib.Asyncseq
  open Frduino.Lib.Io

  /// <summary>
  /// <c>Io.with_open outpin (fun outchan
  /// -> x)</c> opens a channel <c>outchan</c>
  /// at pin <c>outpin</c> and returns
  /// <c>x</c>.
  /// </summary>
  val with_open<'T, 'K> : pinkind -> (t -> M<'T, 'K>) -> M<'T, 'K>

  /// <summary>
  /// <c>Io.bit_write to_chan value</c>
  /// writes a binary bit <c>value</c> to
  /// <c>to_chan</c>.
  /// </summary>
  val bit_write : t -> (bool expr -> Asyn<unit>)

  val led_builtin : pinkind